1. Field of the Invention
The present invention relates to a semiconductor manufacturing technology, and more particularly, to a wafer sawing method.
2. Description of Related Art
With recent advancement of semiconductors and packaging technologies, the fabrication of micro devices including micro-electromechanical devices or electro-optical devices is currently achieved by adopting a prevailing wafer packaging technique rather than a chip packaging technique. Thereby, packaging costs are reduced, and the requirements for lightweight, slimness, compactness, and small volume are satisfied. Generally, after devices on a wafer are completely manufactured in the wafer packaging process, the wafer is flipped and disposed on a carrier. The devices of each chip on the wafer are bonded to the carrier, so as to form a hermetic space between the carrier and each of the chips. Thereafter, a sawing process is performed on a back surface of the wafer, so as to divide the chips.
Note that a cutting tool is moved along constant sawing paths during a sawing operation implemented on the wafer, and interlacing sawing paths are then formed on the wafer in line with the movement and rotation of a process chamber. Due to lack of a focus point for positioning the cutting tool on the back surface of the wafer, longitudinal standard lines and latitudinal standard lines are required to be formed on the back surface of the wafer at first. Next, the back surface of the wafer is sawed with reference to the longitudinal standard lines and latitudinal standard lines. The bonded chips are then separated by a plurality of longitudinal sawing lines and latitudinal sawing lines.
However, errors arisen from tilt angles or a moving distance of the cutting tool may occur when the cutting tool is moved, and each of the longitudinal sawing lines and each of the latitudinal sawing lines use the previous longitudinal sawing line and the previous latitudinal sawing line as the standard. Accordingly, both the previous longitudinal and latitudinal sawing lines and the aforesaid errors caused by the tilt angles or the moving distance of the cutting tool all pose an impact on each of the longitudinal sawing lines and each of the latitudinal sawing lines when the sawing process is carried out. As such, during the implementation of the wafer sawing process, accumulated errors caused by the tilt angles or the moving distance of the cutting tool are apt to take place after the longitudinal sawing lines and the latitudinal sawing lines are formed, i.e., after the cutting tool longitudinally or latitudinally shifts by an excessive distance. Consequently, when the cutting tool performs the sawing operation on the wafer, it is very much likely to damage the devices or circuits on the chips, resulting in malfunctions of the chips.
On the other hand, the errors occurring in the wafer sawing process may affect the hermetic space between the carrier and each of the chips, resulting in failure to protect the devices on the surfaces of the chips. The devices on the chips may accordingly be contaminated by coolant for the sawing operation or by particles of materials in subsequent processes, reducing process yield of the wafer.